EPM3128ATC100-10NS vs EPM3128AFC256-7N 对比
详细并排对比 EPM3128ATC100-10NS 出自 Intel 和 EPM3128AFC256-7N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM3128ATC100-10NS | EPM3128AFC256-7N |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $6.50 | $19.85 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macro Cells | 128 | 128 |
| User I/Os | 80 | 98 |
| 引脚数量 | 100 | — |
| 封装 | TQFP-100 | 256-BGA (FineLine, FBGA) |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | — |
| Counter Frequency (fCNT) | up to 227.3 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | 3.3 V |
| Supply Voltage - I/O (VCCIO) | 3.3 V or 2.5 V (5.0 V-tolerant inputs) | 3.3 V or 2.5 V |
| Logic-Level Compatibility | 5.0 V, 3.3 V, 2.5 V | — |
| Programmability | In-system (ISP), IEEE Std. 1532 | In-system (ISP), IEEE Std. 1532, JTAG (IEEE Std. 1149.1) |
| Boundary Scan | IEEE 1149.1 JTAG | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| 工作温度 | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (commercial) |
| 安装类型 | Surface Mount | Surface Mount |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Architecture | — | CMOS EEPROM-based MAX |
| Usable Gates | — | 2,500 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Internal fMAX | — | 192.3 MHz |
| Logic Family | — | CMOS |