EPM3128ATC144-5 vs EPM3128ATC100-5 Vergleich

Detaillierter Direktvergleich von EPM3128ATC144-5 von Altera und EPM3128ATC100-5 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM3128ATC144-5 EPM3128ATC100-5
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $4,85 $15,43
Family MAX 3000A CPLD - MAX 3000A
Logic Family CMOS CMOS
Device Type CPLD (Complex Programmable Logic Device) —
Number of Macrocells 128 —
Number of Logic Array Blocks (LABs) 8 —
Number of User I/Os 96 —
Device System Gates 2500 —
Product Terms per Macrocell 32 —
Propagation Delay (tPD) 7.5 ns —
Maximum Internal Frequency 192.3 MHz —
Number of Global Clocks 2 —
Program Memory Type EEPROM (non-volatile) EEPROM
Supply Voltage (Core) 3.3 V —
Multi-Volt I/O Voltage 2.5 V / 3.3 V / 5.0 V tolerant —
In-System Programmability Yes (IEEE Std. 1532 compliant) Yes, IEEE Std. 1532 compliant
JTAG / IEEE 1149.1 Yes (boundary-scan + ISP) —
Betriebstemperatur 0C to +70C (Commercial) 0 °C to 70 °C (Commercial)
Gehäuse TQFP-144 (Plastic, 1.0 mm pitch, 22x22 mm) 100-pin TQFP (Fine Line)
Process Technology 0.30 um CMOS EEPROM, 4 metal layers CMOS EEPROM
RoHS-Status Not Compliant (per Arrow distributor listing) [DATA_NEEDED: RoHS status]
ECCN EAR99 —
HTS Code 8542.31.00.55 —
Series — MAX 3000A
Macrocells — 128
Usable Gates — 2,500
User I/Os — 80
Dedicated Inputs — 4
Pin-to-Pin Delay (tpd) — 5 ns (commercial); 7.5 ns
Maximum Frequency (fCNT) — 192.3 MHz
Supply Voltage (VCCINT/VCCIO) — 3.3 V
Output Drive Voltage — 2.5 V or 3.3 V (programmable)
Input Tolerance — 2.5 V, 3.3 V, 5.0 V tolerant
JTAG Boundary Scan — Yes, IEEE Std. 1149.1
Montageart — Surface Mount

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