EPM3128ATI144-5N vs EPM3128ATC144-7N Vergleich
Detaillierter Direktvergleich von EPM3128ATI144-5N von Altera und EPM3128ATC144-7N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3128ATI144-5N | EPM3128ATC144-7N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,50 | $9,25 |
| Family | MAX 3000A | — |
| Logic Gates | 2,500 gates | — |
| Macro Cells | 128 | — |
| User I/Os | 96 | 96 |
| Maximum Operating Frequency | 192.3 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 5.0 ns | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V nominal) | — |
| I/O Standard | LVCMOS / LVTTL (5.0 V tolerant inputs) | — |
| Programming Interface | JTAG (IEEE 1149.1 BST) - in-system | — |
| Process Technology | 0.30 um CMOS EEPROM | — |
| Configuration Memory | Non-volatile on-chip EEPROM | — |
| Gehäuse | TQFP-144 (20x20 mm, 0.5 mm pitch) | TQFP-144 (20 x 20 mm, 0.5 mm pitch) |
| Montageart | Surface Mount | Surface Mount (SMD/SMT) |
| Betriebstemperatur | -40C to +85C (industrial) | 0 °C to +70 °C (commercial) |
| MSL-Level | 3 (168 hours) | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Lead-free (-7N suffix indicates Pb-free finish) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Series | — | MAX 3000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Architecture | — | EEPROM-based, MAX architecture |
| Number of Macrocells | — | 128 |
| Number of Usable Gates | — | Up to 10,000 |
| Pin-Anzahl | — | 144 |
| Logic Family | — | CMOS |
| Propagation Delay (tPD) | — | 7.5 ns (pin-to-pin, -7 speed grade) |
| Counter Frequency | — | Up to 227.3 MHz |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| In-System Programmability (ISP) | — | Yes, via JTAG (IEEE 1149.1) |
| PCI Compliance | — | Compatible with PCI Local Bus Specification Rev. 2.2 |