EPM3256AQC208-10N vs EPM3256AQI208-10 Vergleich
Detaillierter Direktvergleich von EPM3256AQC208-10N von Altera und EPM3256AQI208-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3256AQI208-10 - MAX 3000A 256-Macro CPLD, 10ns, PQFP-208 | Altera
EPM3256AQI208-10 ObsoleteSpezifikationsvergleich
| Parameter | EPM3256AQC208-10N | EPM3256AQI208-10 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $4,62 | $19,95 |
| Series | MAX 3000A | — |
| Programmable Type | In-System Programmable (EEPROM) | — |
| Number of Macrocells | 256 | — |
| Number of Logic Elements/Blocks | 16 LABs | — |
| Usable Gates | 10,000 | 5,000 |
| Number of I/O Pins | 161 (158 user I/O per Arrow listing) | — |
| Propagation Delay (tpd) | 10 ns (max) | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Supply Voltage - Internal | 3.0 V to 3.6 V (3.3 V typical) | — |
| Betriebstemperatur | 0C to +70C (Commercial) | 0C to +70C (Industrial suffix 'I' per part number) |
| Gehäuse / Bauform | 208-BFQFP / 208-PQFP (28x28 mm) | — |
| Montageart | Surface Mount | Surface Mount |
| ISP Compliance | IEEE Std. 1532 | — |
| Boundary Scan | IEEE Std. 1149.1 (JTAG) | — |
| I/O Tolerance | 5 V tolerant, MultiVolt interface | — |
| RoHS-Status | [DATA_NEEDED: lead-free status - non-RoHS suffix 'N' typically indicates lead-free finish, but datasheet not present in data] | Compliant (per lead-free 'Q' suffix) |
| Family | — | MAX 3000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 256 |
| Logic Elements / LABs | — | 16 Logic Array Blocks |
| User I/Os | — | 161 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Frequency (fCNT) | — | 95.2 MHz |
| Internal Counter Speed | — | Up to 227.3 MHz |
| Supply Voltage - Core | — | 3.3 V |
| I/O Logic Compatibility | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Programmability | — | EEPROM, In-System via JTAG (IEEE 1149.1) |
| PCI Compliance | — | PCI Local Bus Specification Revision 2.2 |
| Gehäuse | — | 208-pin PQFP (Plastic Quad Flat Pack), FQFP code |
| Terminal Form | — | Gull-wing SMD |