EPM3256AQI208-10 vs EPM3256AQC208-10 Vergleich
Detaillierter Direktvergleich von EPM3256AQI208-10 von Altera und EPM3256AQC208-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3256AQI208-10 - MAX 3000A 256-Macro CPLD, 10ns, PQFP-208 | Altera
EPM3256AQI208-10 ObsoleteAltera
EPM3256AQC208-10 - MAX 3000A CPLD 256 Macrocells 10ns 208-PQFP | Intel / Altera
EPM3256AQC208-10 ObsoleteSpezifikationsvergleich
| Parameter | EPM3256AQI208-10 | EPM3256AQC208-10 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $19,95 | $15,20 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 256 | — |
| Usable Gates | 5,000 | 5,000 |
| Logic Elements / LABs | 16 Logic Array Blocks | — |
| User I/Os | 161 | 161 |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency (fCNT) | 95.2 MHz | — |
| Internal Counter Speed | Up to 227.3 MHz | — |
| Supply Voltage - Core | 3.3 V | — |
| I/O Logic Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Programmability | EEPROM, In-System via JTAG (IEEE 1149.1) | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 | — |
| Betriebstemperatur | 0C to +70C (Industrial suffix 'I' per part number) | 0 °C to +70 °C (Commercial) |
| Gehäuse | 208-pin PQFP (Plastic Quad Flat Pack), FQFP code | 208-BFQFP (PQFP, Gull Wing) |
| Terminal Form | Gull-wing SMD | — |
| RoHS-Status | Compliant (per lead-free 'Q' suffix) | [DATA_NEEDED: RoHS status] |
| Montageart | Surface Mount | Surface Mount |
| Logic Family | — | CMOS (EEPROM-based) |
| Macrocells | — | 256 |
| Anzahl der Pins | — | 208 |
| Pin-to-Pin Propagation Delay | — | 10 ns |
| Counter Frequency (max) | — | 227.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Tolerance | — | MultiVolt 2.5 V / 3.3 V / 5.0 V tolerant |
| Programming Interface | — | IEEE 1149.1 JTAG (ISP) |
| PCI-SIG Compliance | — | Yes (speed grades -4, -5, -6, -7, -10) |
| Global Clock Networks | — | 4 (CLK, CLR, OE, GCLK) |