EPM3256AQI208-10 vs EPM3256AQC208-10 对比

详细并排对比 EPM3256AQI208-10 出自 Altera 和 EPM3256AQC208-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3256AQI208-10 EPM3256AQC208-10
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $19.95 $15.20
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 256 —
Usable Gates 5,000 5,000
Logic Elements / LABs 16 Logic Array Blocks —
User I/Os 161 161
Propagation Delay (tPD) 10 ns —
Maximum Frequency (fCNT) 95.2 MHz —
Internal Counter Speed Up to 227.3 MHz —
Supply Voltage - Core 3.3 V —
I/O Logic Compatibility 5.0 V / 3.3 V / 2.5 V (MultiVolt) —
Programmability EEPROM, In-System via JTAG (IEEE 1149.1) —
PCI Compliance PCI Local Bus Specification Revision 2.2 —
工作温度 0C to +70C (Industrial suffix 'I' per part number) 0 °C to +70 °C (Commercial)
封装 208-pin PQFP (Plastic Quad Flat Pack), FQFP code 208-BFQFP (PQFP, Gull Wing)
Terminal Form Gull-wing SMD —
RoHS 状态 Compliant (per lead-free 'Q' suffix) [DATA_NEEDED: RoHS status]
安装类型 Surface Mount Surface Mount
Logic Family — CMOS (EEPROM-based)
Macrocells — 256
引脚数 — 208
Pin-to-Pin Propagation Delay — 10 ns
Counter Frequency (max) — 227.3 MHz
Supply Voltage (VCCINT) — 3.3 V
I/O Tolerance — MultiVolt 2.5 V / 3.3 V / 5.0 V tolerant
Programming Interface — IEEE 1149.1 JTAG (ISP)
PCI-SIG Compliance — Yes (speed grades -4, -5, -6, -7, -10)
Global Clock Networks — 4 (CLK, CLR, OE, GCLK)

数据手册与资源

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