EPM3256ATI144-7N vs EPM3256ATI144-10 Vergleich
Detaillierter Direktvergleich von EPM3256ATI144-7N von Altera und EPM3256ATI144-10 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3256ATI144-7N - 256-Macrocell MAX 3000A CPLD, 7.5ns, TQFP-144 | Altera
EPM3256ATI144-7N ObsoleteSpezifikationsvergleich
| Parameter | EPM3256ATI144-7N | EPM3256ATI144-10 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,95 | $0,00 |
| Family | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 256 | — |
| Usable Gates | 5,000 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 116 | — |
| Propagation Delay (tPD) | 7.5 ns (typical) | — |
| Maximum Internal Frequency | 126.6 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | — |
| MultiVolt I/O Logic Levels | 5.0 V / 3.3 V / 2.5 V | — |
| Programming Technology | EEPROM (in-system programmable) | — |
| JTAG / ISP | IEEE Std. 1532 compliant | — |
| Boundary Scan | IEEE Std. 1149.1 (JTAG) | — |
| Hot-Socketing Support | Yes | — |
| Gehäuse | TQFP-144 (20 x 20 mm, 0.5 mm pitch) | 144-pin TQFP (20x20 mm) |
| Betriebstemperatur | -40C to +85C (industrial) | -40°C to +85°C (industrial) |
| RoHS-Status | Compliant (lead-free) | — |
| Series | — | MAX 3000A |
| Programmable Type | — | In-System Programmable (ISP), EEPROM-based |
| Number of Macrocells | — | 256 |
| Number of Logic Elements / Blocks | — | 16 LABs (Logic Array Blocks) |
| Number of Gates | — | 5,000 typical usable gates |
| Number of User I/O | — | 116 |
| Propagation Delay (tpd max) | — | 10 ns |
| Maximum Frequency (fmax) | — | 95.2 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V (3.3 V nominal) |
| I/O Voltage Support | — | MultiVolt: 1.8 V / 2.5 V / 3.3 V / 5.0 V mixed |
| Logic Family | — | CMOS, EEPROM-based |
| Montageart | — | Surface Mount |
| Programming Interface | — | JTAG (IEEE 1149.1) and IEEE Std. 1532 ISP |
| Compliance | — | IEEE Std. 1532 ISP, PCI-compatible I/O |
| Lebenszyklusstatus | — | Obsolete (per HighqualityPCB listing) |