EPM3256ATI144-7N vs EPM3256ATI144-10 对比

详细并排对比 EPM3256ATI144-7N 出自 Altera 和 EPM3256ATI144-10 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3256ATI144-7N EPM3256ATI144-10
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $10.95 $0.00
Family MAX 3000A —
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 256 —
Usable Gates 5,000 —
Logic Array Blocks (LABs) 16 —
Maximum User I/O Pins 116 —
Propagation Delay (tPD) 7.5 ns (typical) —
Maximum Internal Frequency 126.6 MHz —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 3.3 V or 2.5 V —
MultiVolt I/O Logic Levels 5.0 V / 3.3 V / 2.5 V —
Programming Technology EEPROM (in-system programmable) —
JTAG / ISP IEEE Std. 1532 compliant —
Boundary Scan IEEE Std. 1149.1 (JTAG) —
Hot-Socketing Support Yes —
封装 TQFP-144 (20 x 20 mm, 0.5 mm pitch) 144-pin TQFP (20x20 mm)
工作温度 -40C to +85C (industrial) -40°C to +85°C (industrial)
RoHS 状态 Compliant (lead-free) —
Series — MAX 3000A
Programmable Type — In-System Programmable (ISP), EEPROM-based
Number of Macrocells — 256
Number of Logic Elements / Blocks — 16 LABs (Logic Array Blocks)
Number of Gates — 5,000 typical usable gates
Number of User I/O — 116
Propagation Delay (tpd max) — 10 ns
Maximum Frequency (fmax) — 95.2 MHz
Supply Voltage (VCCINT) — 3.0 V to 3.6 V (3.3 V nominal)
I/O Voltage Support — MultiVolt: 1.8 V / 2.5 V / 3.3 V / 5.0 V mixed
Logic Family — CMOS, EEPROM-based
安装类型 — Surface Mount
Programming Interface — JTAG (IEEE 1149.1) and IEEE Std. 1532 ISP
Compliance — IEEE Std. 1532 ISP, PCI-compatible I/O
生命周期状态 — Obsolete (per HighqualityPCB listing)

数据手册与资源

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