EPM3512AFC256-10 vs EPM3512AFC256-23 Vergleich
Detaillierter Direktvergleich von EPM3512AFC256-10 von Altera und EPM3512AFC256-23 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3512AFC256-23 - MAX 3000A CPLD, 512 Macrocells, 256-BGA | Altera
EPM3512AFC256-23 ObsoleteSpezifikationsvergleich
| Parameter | EPM3512AFC256-10 | EPM3512AFC256-23 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,50 | $15,75 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 (32 macrocells each) |
| Usable Gates | 10,000 | 10,000 |
| Maximum I/O Pins | 208 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 87 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Voltage Tolerance | 5-V tolerant | — |
| Programmable Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) | — |
| Gehäuse | 256-pin FBGA | 256-ball FineLine BGA (FC256), 17 mm x 17 mm |
| Betriebstemperaturbereich | [DATA_NEEDED: industrial/commercial operating temperature range] | — |
| Pin-Anzahl | 256 | — |
| Montageart | Surface Mount | Surface Mount (BGA) |
| RoHS-Status | unknown | — |
| Architecture | MAX (Multiple Array matriX) EEPROM-based | — |
| Maximum Operating Frequency | — | 178.6 MHz |
| Propagation Delay (tPD) | — | 5.5 ns |
| Pin-to-Pin Delay | — | 23 ns |
| I/O Supply Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| User I/O Pins | — | [DATA_NEEDED: user I/O count for FC256] |
| Programming Interface | — | JTAG (IEEE Std. 1149.1) / ISP |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| Betriebstemperatur | — | [DATA_NEEDED: operating temperature grade] |