EPM3512AFC256-10N vs EPM3512AFC256-10 Vergleich
Detaillierter Direktvergleich von EPM3512AFC256-10N von Altera und EPM3512AFC256-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3512AFC256-10N | EPM3512AFC256-10 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $43,22 | $17,50 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Usable Gates | 10000 | 10,000 |
| User I/O Pins | 208 | — |
| Logic Array Blocks (LABs) | [DATA_NEEDED: number of LABs] | 16 |
| Operating Frequency (fMAX) | [DATA_NEEDED: fMAX MHz] | — |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns |
| Setup Time (tSU) | 4.5 ns | — |
| VCCINT (Core Supply) | 3.3 V | — |
| VCCIO (I/O Supply) | 3.3 V or 2.5 V | — |
| Technology | CMOS EEPROM-based, non-volatile | — |
| Operating Temperature (Commercial) | 0 C to +70 C | — |
| Gehäuse | 256-ball FBGA (17 mm x 17 mm) | 256-pin FBGA |
| ISP Interface | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 | — |
| Montageart | Surface Mount (BGA) | Surface Mount |
| MSL-Level | [DATA_NEEDED: MSL rating] | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | unknown |
| Maximum I/O Pins | — | 208 |
| Maximum Counter Frequency | — | 87 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage Tolerance | — | 5-V tolerant |
| Programmable Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) |
| Betriebstemperaturbereich | — | [DATA_NEEDED: industrial/commercial operating temperature range] |
| Pin-Anzahl | — | 256 |
| Architecture | — | MAX (Multiple Array matriX) EEPROM-based |