EPM3512AFC256-2 vs EPM3512AFC256-23 Vergleich
Detaillierter Direktvergleich von EPM3512AFC256-2 von Altera und EPM3512AFC256-23 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3512AFC256-23 - MAX 3000A CPLD, 512 Macrocells, 256-BGA | Altera
EPM3512AFC256-23 ObsoleteSpezifikationsvergleich
| Parameter | EPM3512AFC256-2 | EPM3512AFC256-23 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $14,85 | $15,75 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 (32 macrocells each) |
| Maximum User I/O Pins | 212 | — |
| Propagation Delay (tPD, -2 grade) | [DATA_NEEDED: tPD ns] | — |
| Maximum Operating Frequency | [DATA_NEEDED: fMAX MHz] | 178.6 MHz |
| Core Supply Voltage | 3.3 V | — |
| I/O Output Drive Voltage | 2.5 V or 3.3 V (MultiVolt) | — |
| Input Tolerance | 2.5 V, 3.3 V, 5.0 V tolerant | — |
| Gehäuse | BGA-256 (FineLine BGA) | 256-ball FineLine BGA (FC256), 17 mm x 17 mm |
| Ball Pitch | 1.0 mm | — |
| Programming Interface | JTAG (IEEE Std 1149.1) / ByteBlaster | JTAG (IEEE Std. 1149.1) / ISP |
| Process Technology | 0.30 um CMOS EEPROM | 0.30 µm CMOS EEPROM |
| Betriebstemperatur | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature grade] |
| RoHS-Status | [DATA_NEEDED: RoHS status] | — |
| Speed Grade | -2 | — |
| Usable Gates | — | 10,000 |
| Propagation Delay (tPD) | — | 5.5 ns |
| Pin-to-Pin Delay | — | 23 ns |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| User I/O Pins | — | [DATA_NEEDED: user I/O count for FC256] |
| Montageart | — | Surface Mount (BGA) |