EPM3512AFC256-23 vs EPM3512AFC256-2N Vergleich
Detaillierter Direktvergleich von EPM3512AFC256-23 von Altera und EPM3512AFC256-2N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3512AFC256-23 - MAX 3000A CPLD, 512 Macrocells, 256-BGA | Altera
EPM3512AFC256-23 ObsoleteSpezifikationsvergleich
| Parameter | EPM3512AFC256-23 | EPM3512AFC256-2N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $15,75 | $25,80 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | — |
| Logic Array Blocks (LABs) | 16 (32 macrocells each) | 32 |
| Maximum Operating Frequency | 178.6 MHz | [DATA_NEEDED: fMAX in MHz] |
| Propagation Delay (tPD) | 5.5 ns | [DATA_NEEDED: tPD in ns] |
| Pin-to-Pin Delay | 23 ns | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| User I/O Pins | [DATA_NEEDED: user I/O count for FC256] | — |
| Gehäuse | 256-ball FineLine BGA (FC256), 17 mm x 17 mm | 256-ball FineLine BGA (FC-256) |
| Programming Interface | JTAG (IEEE Std. 1149.1) / ISP | — |
| Process Technology | 0.30 µm CMOS EEPROM | 0.30 µm CMOS EEPROM |
| Betriebstemperatur | [DATA_NEEDED: operating temperature grade] | — |
| Montageart | Surface Mount (BGA) | Surface Mount (BGA) |
| Maximum User I/O Pins | — | 212 |
| Configuration Memory | — | Non-volatile EEPROM |
| In-System Programmability | — | IEEE Std. 1532 JTAG |
| VCCINT (Core Supply) | — | 3.3 V |
| VCCIO (I/O Supply) | — | 2.5 V / 3.3 V / 5.0 V MultiVolt |
| PCI Compliance | — | 3.3 V PCI-compliant |
| Operating Temperature (Commercial) | — | 0 °C to +70 °C |
| RoHS-Status | — | Compliant |
| Lead-Free | — | Yes |