EPM3512AFC256-3N vs EPM3512AFC256-5C Vergleich
Detaillierter Direktvergleich von EPM3512AFC256-3N von Altera und EPM3512AFC256-5C von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3512AFC256-5C - MAX 3000A CPLD, 512 Macrocells, 256-BGA | Altera
EPM3512AFC256-5C ObsoleteSpezifikationsvergleich
| Parameter | EPM3512AFC256-3N | EPM3512AFC256-5C |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $23,40 | $28,95 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | 10,000 |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum Operating Frequency | 116.3 MHz | 95.2 MHz |
| Pin-to-Pin Delay (tPD) | 3.5 ns (speed grade -3) | 5 ns |
| Speed Grade | -3 (slowest in family) | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Gehäuse | 256-ball FineLine BGA (FC-256) | 256-ball FBGA, 17 mm × 17 mm, 1.0 mm pitch |
| Montageart | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / IEEE Std. 1532 ISP | IEEE Std. 1532 / JTAG (4-wire) in-system programmable |
| Configuration Memory | Non-volatile EEPROM | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature grade] | 0 °C to +70 °C (commercial, "C" grade) |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| I/O Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (banked MultiVolt I/O) |
| User I/O Pins | — | 212 (max) |
| Technology | — | EEPROM-based macrocell, non-volatile |