EPM3512AFC256-5C vs EPM3256AFC256-10 Vergleich
Detaillierter Direktvergleich von EPM3512AFC256-5C von Altera und EPM3256AFC256-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3512AFC256-5C - MAX 3000A CPLD, 512 Macrocells, 256-BGA | Altera
EPM3512AFC256-5C ObsoleteAltera
EPM3256AFC256-10 - 256-Macro CPLD MAX 3000A | Intel / Altera | FBGA-256
EPM3256AFC256-10 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM3512AFC256-5C | EPM3256AFC256-10 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $28,95 | $19,95 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | — |
| Usable Gates | 10,000 | 5,000 |
| Maximum Operating Frequency | 95.2 MHz | — |
| Pin-to-Pin Delay (tPD) | 5 ns | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (banked MultiVolt I/O) | — |
| User I/O Pins | 212 (max) | — |
| Gehäuse | 256-ball FBGA, 17 mm × 17 mm, 1.0 mm pitch | 256-ball FBGA (Fine-Line BGA) |
| Betriebstemperatur | 0 °C to +70 °C (commercial, "C" grade) | 0°C to +70°C (Commercial) |
| Programming Interface | IEEE Std. 1532 / JTAG (4-wire) in-system programmable | — |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Technology | EEPROM-based macrocell, non-volatile | — |
| Logic Family | — | CMOS (EEPROM-based) |
| Macro Cells | — | 256 |
| Logic Array Blocks (LABs) | — | 16 (16 macrocells each) |
| Maximum User I/Os | — | 161 |
| Propagation Delay (tPD) | — | 10 ns |
| Internal Counter Frequency (fCNT) | — | 95.2 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage Tolerance | — | 5.0 V tolerant |
| In-System Programmability | — | Yes (3.3 V ISP via JTAG IEEE 1149.1) |
| Pitch | — | [DATA_NEEDED: BGA ball pitch] |