EPM3512AFC256-5C vs EPM3256AFC256-10 对比

详细并排对比 EPM3512AFC256-5C 出自 Altera 和 EPM3256AFC256-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM3256AFC256-10 EPM3256AFC256-10 - 256-Macro CPLD MAX 3000A | Intel / Altera | FBGA-256

EPM3256AFC256-10 - 256-Macro CPLD MAX 3000A | Intel / Altera | FBGA-256

EPM3256AFC256-10 ⚠ 最后一次采购

规格对比

参数 EPM3512AFC256-5C EPM3256AFC256-10
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $28.95 $19.95
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 —
Usable Gates 10,000 5,000
Maximum Operating Frequency 95.2 MHz —
Pin-to-Pin Delay (tPD) 5 ns —
Supply Voltage - Core (VCCINT) 3.3 V —
I/O Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (banked MultiVolt I/O) —
User I/O Pins 212 (max) —
封装 256-ball FBGA, 17 mm × 17 mm, 1.0 mm pitch 256-ball FBGA (Fine-Line BGA)
工作温度 0 °C to +70 °C (commercial, "C" grade) 0°C to +70°C (Commercial)
Programming Interface IEEE Std. 1532 / JTAG (4-wire) in-system programmable —
安装类型 Surface Mount Surface Mount
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Technology EEPROM-based macrocell, non-volatile —
Logic Family — CMOS (EEPROM-based)
Macro Cells — 256
Logic Array Blocks (LABs) — 16 (16 macrocells each)
Maximum User I/Os — 161
Propagation Delay (tPD) — 10 ns
Internal Counter Frequency (fCNT) — 95.2 MHz
Supply Voltage (VCCINT) — 3.3 V
I/O Voltage Tolerance — 5.0 V tolerant
In-System Programmability — Yes (3.3 V ISP via JTAG IEEE 1149.1)
Pitch — [DATA_NEEDED: BGA ball pitch]

数据手册与资源

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