EPM3512AFI256-10N vs EPM3512AFC256-7N Vergleich
Detaillierter Direktvergleich von EPM3512AFI256-10N von Altera und EPM3512AFC256-7N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3512AFI256-10N - 512-Macro MAX 3000A CPLD, 256-FBGA | Intel/Altera
EPM3512AFI256-10N ⚠ Letzte BestellmöglichkeitAltera
EPM3512AFC256-7N - MAX 3000A CPLD, 512 Macrocells, 208 I/O | Altera
EPM3512AFC256-7N ObsoleteSpezifikationsvergleich
| Parameter | EPM3512AFI256-10N | EPM3512AFC256-7N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $21,75 | $61,00 |
| Family | MAX 3000A | MAX 3000A |
| Series | EPM3512 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Architecture | CMOS EEPROM-based, MAX architecture | — |
| Number of Macrocells | 512 | — |
| Number of Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | Up to 10,000 | 10,000 |
| Number of User I/O | 208 | — |
| Total Pins | 256 | — |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | 3.3 V |
| I/O Supply Voltage (VCCIO) | 2.5 V or 3.3 V (5.0 V tolerant inputs) | 3.3 V or 2.5 V |
| MultiVolt I/O Support | 5.0 V / 3.3 V / 2.5 V | — |
| In-System Programmability | Yes - IEEE Std 1532 compliant | IEEE Std. 1532 compliant |
| JTAG Boundary Scan | Yes - IEEE 1149.1 | — |
| Program Memory | EEPROM (non-volatile) | — |
| Gehäuse | 256-ball FineLine BGA (FBGA-256) | 256-pin FineLine BGA (FBGA-256), 1.0 mm pitch |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperaturbereich | -40 °C to +85 °C (industrial) | — |
| RoHS-Status | Compliant | [DATA_NEEDED: RoHS status] |
| Speed Grade | -10 (10 ns tPD) | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 512 |
| User I/Os | — | 208 |
| Logic Blocks | — | 16 (32 macrocells each) |
| Propagation Delay (tPD) | — | 7.5 ns |
| Maximum Internal Frequency (fMAX) | — | 116.3 MHz |
| 5V Tolerant I/O | — | Yes |
| Programming Interface | — | JTAG (IEEE 1149.1) |
| Process Technology | — | CMOS EEPROM, 0.30 um |
| Betriebstemperatur | — | 0 C to 70 C (commercial) |