EPM3512AFI256-7N vs EPM3512AFI256-10 Vergleich
Detaillierter Direktvergleich von EPM3512AFI256-7N von Altera und EPM3512AFI256-10 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3512AFI256-7N - MAX 3000A CPLD, 512 Macrocells | Intel / Altera
EPM3512AFI256-7N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM3512AFI256-7N | EPM3512AFI256-10 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $27,95 | $18,75 |
| Family | MAX 3000A | MAX 3000A |
| Device Logic Elements / Macrocells | 512 macrocells | — |
| Typical Usable Gates | 10,000 gates | — |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | [DATA_NEEDED: user I/O count] | — |
| Maximum Operating Frequency (fMAX) | 116.3 MHz | — |
| Pin-to-Pin Delay (tPD, speed grade -7) | approximately 7.5 ns | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| MultiVolt I/O Levels | 2.5 V / 3.3 V / 5 V mixed | 5.0 V / 3.3 V / 2.5 V |
| Configuration Memory | Non-volatile EEPROM | — |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) | — |
| Gehäuse | 256-ball FBGA | FBGA-256 (FineLine BGA, 256 balls) |
| Betriebstemperaturbereich | -40C to +85C (industrial) | — |
| Lead-Free / RoHS | Yes ('N' suffix, lead-free) | — |
| Design Software | Quartus II (legacy MAX 3000A support) | — |
| Speed Grade | -7 | — |
| Montageart | Surface Mount (BGA) | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Equivalent Gates | — | 10,000 |
| Macrocells | — | 512 |
| User I/Os | — | 208 |
| Pin-to-Pin Logic Delay (tPD) | — | 4.5 ns |
| Maximum Counter Frequency | — | 227.3 MHz |
| Propagation Delay | — | 7.5 ns (max, per chipdig summary) |
| Core Voltage | — | 3.3 V |
| Process Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes, IEEE Std. 1532 (3.3 V ISP) |
| Betriebstemperatur | — | 0C to +70C (commercial) |
| Logic Family | — | CMOS |
| RoHS-Status | — | [DATA_NEEDED: rohs_status] |
| Versorgungsspannung | — | 3.3 V (core); MultiVolt I/O to 5.0 V |