EPM3512AFI256-7N vs EPM3512AFI256-10 对比

详细并排对比 EPM3512AFI256-7N 出自 Altera 和 EPM3512AFI256-10 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM3512AFI256-7N EPM3512AFI256-7N - MAX 3000A CPLD, 512 Macrocells | Intel / Altera

EPM3512AFI256-7N - MAX 3000A CPLD, 512 Macrocells | Intel / Altera

EPM3512AFI256-7N ⚠ 最后一次采购

规格对比

参数 EPM3512AFI256-7N EPM3512AFI256-10
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 有效
库存状态 有库存 有库存
单价(USD) $27.95 $18.75
Family MAX 3000A MAX 3000A
Device Logic Elements / Macrocells 512 macrocells —
Typical Usable Gates 10,000 gates —
Logic Array Blocks (LABs) 16 —
Maximum User I/O Pins [DATA_NEEDED: user I/O count] —
Maximum Operating Frequency (fMAX) 116.3 MHz —
Pin-to-Pin Delay (tPD, speed grade -7) approximately 7.5 ns —
Supply Voltage (VCCINT) 3.3 V —
MultiVolt I/O Levels 2.5 V / 3.3 V / 5 V mixed 5.0 V / 3.3 V / 2.5 V
Configuration Memory Non-volatile EEPROM —
Programming Interface IEEE 1149.1 JTAG (in-system programmable) —
封装 256-ball FBGA FBGA-256 (FineLine BGA, 256 balls)
工作温度范围 -40C to +85C (industrial) —
Lead-Free / RoHS Yes ('N' suffix, lead-free) —
Design Software Quartus II (legacy MAX 3000A support) —
Speed Grade -7 —
安装类型 Surface Mount (BGA) —
Product Type — CPLD (Complex Programmable Logic Device)
Equivalent Gates — 10,000
Macrocells — 512
User I/Os — 208
Pin-to-Pin Logic Delay (tPD) — 4.5 ns
Maximum Counter Frequency — 227.3 MHz
Propagation Delay — 7.5 ns (max, per chipdig summary)
Core Voltage — 3.3 V
Process Technology — CMOS EEPROM
In-System Programmability — Yes, IEEE Std. 1532 (3.3 V ISP)
工作温度 — 0C to +70C (commercial)
Logic Family — CMOS
RoHS 状态 — [DATA_NEEDED: rohs_status]
电源电压 — 3.3 V (core); MultiVolt I/O to 5.0 V

数据手册与资源

浏览全部产品 创建 BOM 获取报价