EPM3512AFI256-7N vs EPM3512AFI256-10N Vergleich
Detaillierter Direktvergleich von EPM3512AFI256-7N von Altera und EPM3512AFI256-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3512AFI256-7N - MAX 3000A CPLD, 512 Macrocells | Intel / Altera
EPM3512AFI256-7N ⚠ Letzte BestellmöglichkeitAltera
EPM3512AFI256-10N - 512-Macro MAX 3000A CPLD, 256-FBGA | Intel/Altera
EPM3512AFI256-10N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM3512AFI256-7N | EPM3512AFI256-10N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $27,95 | $21,75 |
| Family | MAX 3000A | MAX 3000A |
| Device Logic Elements / Macrocells | 512 macrocells | — |
| Typical Usable Gates | 10,000 gates | — |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | [DATA_NEEDED: user I/O count] | — |
| Maximum Operating Frequency (fMAX) | 116.3 MHz | — |
| Pin-to-Pin Delay (tPD, speed grade -7) | approximately 7.5 ns | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| MultiVolt I/O Levels | 2.5 V / 3.3 V / 5 V mixed | — |
| Configuration Memory | Non-volatile EEPROM | — |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) | — |
| Gehäuse | 256-ball FBGA | 256-ball FineLine BGA (FBGA-256) |
| Betriebstemperaturbereich | -40C to +85C (industrial) | -40 °C to +85 °C (industrial) |
| Lead-Free / RoHS | Yes ('N' suffix, lead-free) | — |
| Design Software | Quartus II (legacy MAX 3000A support) | — |
| Speed Grade | -7 | -10 (10 ns tPD) |
| Montageart | Surface Mount (BGA) | Surface Mount |
| Series | — | EPM3512 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Architecture | — | CMOS EEPROM-based, MAX architecture |
| Number of Macrocells | — | 512 |
| Number of Logic Array Blocks (LABs) | — | 16 |
| Usable Gates | — | Up to 10,000 |
| Number of User I/O | — | 208 |
| Total Pins | — | 256 |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 227.3 MHz |
| Core Supply Voltage (VCCINT) | — | 3.3 V (3.0 V to 3.6 V) |
| I/O Supply Voltage (VCCIO) | — | 2.5 V or 3.3 V (5.0 V tolerant inputs) |
| MultiVolt I/O Support | — | 5.0 V / 3.3 V / 2.5 V |
| In-System Programmability | — | Yes - IEEE Std 1532 compliant |
| JTAG Boundary Scan | — | Yes - IEEE 1149.1 |
| Program Memory | — | EEPROM (non-volatile) |
| RoHS-Status | — | Compliant |