EPM3512AQ208-10N vs EPM3256AQI208-10N Vergleich
Detaillierter Direktvergleich von EPM3512AQ208-10N von Altera und EPM3256AQI208-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3512AQ208-10N | EPM3256AQI208-10N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $21,40 | $9,75 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 256 |
| Usable Gates | 10,000 | 5,000 |
| User I/Os | 172 | 161 |
| Logic Array Blocks (LABs) | 32 | — |
| Gehäuse | 208-pin PQFP | 208-pin PQFP (Plastic Quad Flat Pack) |
| Speed Grade | -10 (10 ns pin-to-pin delay) | -10 |
| Pin-to-Pin Delay (tPD) | 4.5 ns (typical) | — |
| Maximum Frequency (fCNT) | 227.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V, 3.3 V, or 5.0 V | — |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Programming Interface | IEEE Std. 1532 (JTAG) ISP | JTAG (IEEE 1149.1) ISP |
| Operating Temperature (Industrial) | -40 C to +85 C | — |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | unknown | Non-compliant (Pb-bearing PQFP package) |
| Logic Elements / LABs | — | 16 Logic Array Blocks (LABs) |
| Propagation Delay (tPD) | — | 10 ns |
| Counter Frequency | — | 118.7 MHz (max, -10 speed grade) |
| Supply Voltage - Core | — | 3.3 V |
| I/O Logic Level Compatibility | — | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) |
| Betriebstemperatur | — | -40 C to +85 C (industrial) |
| Hot-Socketing Support | — | Yes |