EPM3512AQC208-10N vs EPM3512AQC208-10NS Vergleich
Detaillierter Direktvergleich von EPM3512AQC208-10N von Intel und EPM3512AQC208-10NS von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3512AQC208-10N | EPM3512AQC208-10NS |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $42,80 | $32,40 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | — |
| Usable Gates | Up to 10,000 | 10,000 |
| Logic Array Blocks (LABs) | 16 | 12 |
| User I/Os | 172 | 172 |
| Gehäuse | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin PQFP |
| Versorgungsspannung | 3.3 V | — |
| Pin-to-Pin Delay | 4.5 ns (-10 speed grade) | — |
| Maximum Internal Frequency | 227.3 MHz | — |
| Speed Grade | -10 | — |
| Process Technology | CMOS EEPROM | — |
| In-System Programming | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant | — |
| I/O Standards | MultiVolt (1.8V / 2.5V / 3.3V) | — |
| Betriebstemperatur | 0 C to 70 C (commercial) | 0C to +70C (commercial) |
| RoHS-Status | [DATA_NEEDED: RoHS status not in verified web data] | [DATA_NEEDED: rohs status] |
| Macro Cells | — | 512 |
| Pin-to-Pin Delay (tPD) | — | 10 ns (speed grade -10) |
| Internal Counter Frequency | — | 227.3 MHz max |
| Propagation Delay | — | 7.5 ns (datasheet figure) |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Logic Family | — | CMOS, EEPROM-based |
| Configuration | — | Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532) |
| ISP Standard | — | IEEE Std. 1532 |
| Montageart | — | Surface Mount |