EPM3512AQC208-3N vs EPM3512AQC208-10NS Vergleich
Detaillierter Direktvergleich von EPM3512AQC208-3N von Altera und EPM3512AQC208-10NS von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3512AQC208-3N | EPM3512AQC208-10NS |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $16,40 | $32,40 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | — |
| User I/O Pins | 172 | — |
| Logic Array Blocks (LABs) | 16 | 12 |
| Macrocells per LAB | 32 | — |
| Pin-to-Pin Logic Delay | 3 ns (speed grade -3) | — |
| Global Clock Setup Time | [DATA_NEEDED: actual tSU at 3 ns grade] | — |
| Core Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Supply Voltage (VCCIO) | 3.3 V (MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Gehäuse | PQFP-208 | 208-pin PQFP |
| Montageart | Surface Mount | Surface Mount |
| Programming Technology | EEPROM (non-volatile, in-system programmable) | — |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| ISP Compliance | IEEE Std. 1532 | — |
| RoHS-Status | [DATA_NEEDED: not stated in retrieved snippets] | [DATA_NEEDED: rohs status] |
| Lead-Free / Halogen-Free | [DATA_NEEDED] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 512 |
| Usable Gates | — | 10,000 |
| User I/Os | — | 172 |
| Pin-to-Pin Delay (tPD) | — | 10 ns (speed grade -10) |
| Internal Counter Frequency | — | 227.3 MHz max |
| Propagation Delay | — | 7.5 ns (datasheet figure) |
| Logic Family | — | CMOS, EEPROM-based |
| Configuration | — | Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532) |
| ISP Standard | — | IEEE Std. 1532 |