EPM3512AQC210-10 vs EPM3256AQC208-10 Vergleich
Detaillierter Direktvergleich von EPM3512AQC210-10 von Altera und EPM3256AQC208-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3256AQC208-10 - MAX 3000A CPLD 256 Macrocells 10ns 208-PQFP | Intel / Altera
EPM3256AQC208-10 ObsoleteSpezifikationsvergleich
| Parameter | EPM3512AQC210-10 | EPM3256AQC208-10 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $25,40 | $15,20 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Macrocells | 512 | — |
| Logic Array Blocks (LABs) | 16 (32 macrocells each) | — |
| Maximum User I/O Pins | 172 | — |
| Speed Grade | -10 (10 ns tPD) | — |
| Pin-to-Pin Propagation Delay (tPD1, max) | 10 ns | — |
| Maximum Operating Frequency (fCNT) | 125 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| Supply Voltage - I/O (VCCIO) | 3.3 V or 2.5 V | — |
| Input Voltage Tolerance | 5.0 V tolerant | — |
| Programmable Technology | EEPROM (in-system programmable) | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | IEEE 1149.1 JTAG (ISP) |
| Gehäuse | PQFP-210 | 208-BFQFP (PQFP, Gull Wing) |
| Betriebstemperatur | 0C to +70C (commercial) | 0 °C to +70 °C (Commercial) |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: rohs_compliance_status] | [DATA_NEEDED: RoHS status] |
| Logic Family | — | CMOS (EEPROM-based) |
| Macrocells | — | 256 |
| Usable Gates | — | 5,000 |
| User I/Os | — | 161 |
| Anzahl der Pins | — | 208 |
| Pin-to-Pin Propagation Delay | — | 10 ns |
| Counter Frequency (max) | — | 227.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Tolerance | — | MultiVolt 2.5 V / 3.3 V / 5.0 V tolerant |
| PCI-SIG Compliance | — | Yes (speed grades -4, -5, -6, -7, -10) |
| Global Clock Networks | — | 4 (CLK, CLR, OE, GCLK) |