EPM3512AQC210-7 vs EPM3512AQI210-10 Vergleich
Detaillierter Direktvergleich von EPM3512AQC210-7 von Altera und EPM3512AQI210-10 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3512AQC210-7 | EPM3512AQI210-10 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $21,85 | $19,95 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/O Pins | 172 | 212 |
| Dedicated Input Pins | 12 | — |
| Gehäuse | PQFP-208 | PQFP-210 |
| Pin-Anzahl | 208 | — |
| Montageart | Surface Mount | Surface Mount |
| Operating Voltage (Core) | 3.3 V | — |
| Min Supply Voltage | 3.0 V | — |
| Max Supply Voltage | 3.6 V | — |
| I/O Voltage Support | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) | — |
| Pin-to-Pin Delay | 7 ns (speed grade -7) | — |
| Speed Grade | 7 ns | — |
| In-System Programmability | Yes (JTAG, IEEE 1149.1) | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) |
| Non-Volatile Configuration | Yes (EEPROM-based) | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: rohs_status] |
| Usable Gates | — | 10,000 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage (MultiVolt) | — | 1.8 V / 2.5 V / 3.3 V / 5 V tolerant |
| Programming Interface | — | JTAG (IEEE 1149.1 / IEEE 1532) |
| In-System Programmable | — | Yes (ISP via JTAG) |
| Configuration Memory | — | Non-volatile EEPROM |