EPM5016DC-15 vs EPM5032DC-15 Vergleich
Detaillierter Direktvergleich von EPM5016DC-15 von Altera und EPM5032DC-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM5032DC-15 - 600-Gate, 32-Macrocell UV PLD | Altera MAX 5000 | DIP-28
EPM5032DC-15 ObsoleteSpezifikationsvergleich
| Parameter | EPM5016DC-15 | EPM5032DC-15 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,75 | $9,95 |
| Device Family | MAX 5000 | — |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 16 | 32 |
| Logic Array Blocks (LABs) | 2 | — |
| Dedicated Inputs | 4 | — |
| User I/O Pins | 12 | — |
| Pin-to-Pin Delay (tpd) | 15 ns | — |
| Maximum Frequency (fmax) | 71 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V (nominal) |
| Programming Voltage (VPP) | 12.75 V | — |
| Betriebstemperatur | 0 °C to 70 °C (commercial) | 0C to +70C (commercial) |
| Gehäuse | Ceramic DIP-24 (windowed) | CERDIP-28 (windowed, through-hole) |
| Montageart | Through-Hole | Through-Hole (DIP) |
| Process Technology | CMOS EPROM | CMOS |
| Configuration Memory | Non-volatile UV-erasable EPROM | — |
| RoHS-Status | [DATA_NEEDED: RoHS status - pre-RoHS era part, likely non-compliant] | [DATA_NEEDED: RoHS status] |
| Lead Finish | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 5000 |
| Device Type | — | UV-erasable EPLD (PAL-type CMOS) |
| Usable Gates | — | 600 |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Toggle Frequency (fMAX) | — | 83.3 MHz |
| Logic Family | — | CMOS, TTL-compatible I/O |
| Programmable Pins | — | 16 bidirectional I/O + 4 dedicated input = 20 |
| Total Package Pins | — | 28 |
| Erasure Method | — | UV light through ceramic quartz window |
| Lead-Free | — | unknown |