EPM5016DC-15 vs EPM5032DC-15 对比
详细并排对比 EPM5016DC-15 出自 Altera 和 EPM5032DC-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM5032DC-15 - 600-Gate, 32-Macrocell UV PLD | Altera MAX 5000 | DIP-28
EPM5032DC-15 Obsolete规格对比
| 参数 | EPM5016DC-15 | EPM5032DC-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $10.75 | $9.95 |
| Device Family | MAX 5000 | — |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 16 | 32 |
| Logic Array Blocks (LABs) | 2 | — |
| Dedicated Inputs | 4 | — |
| User I/O Pins | 12 | — |
| Pin-to-Pin Delay (tpd) | 15 ns | — |
| Maximum Frequency (fmax) | 71 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V (nominal) |
| Programming Voltage (VPP) | 12.75 V | — |
| 工作温度 | 0 °C to 70 °C (commercial) | 0C to +70C (commercial) |
| 封装 | Ceramic DIP-24 (windowed) | CERDIP-28 (windowed, through-hole) |
| 安装类型 | Through-Hole | Through-Hole (DIP) |
| Process Technology | CMOS EPROM | CMOS |
| Configuration Memory | Non-volatile UV-erasable EPROM | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status - pre-RoHS era part, likely non-compliant] | [DATA_NEEDED: RoHS status] |
| Lead Finish | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 5000 |
| Device Type | — | UV-erasable EPLD (PAL-type CMOS) |
| Usable Gates | — | 600 |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Toggle Frequency (fMAX) | — | 83.3 MHz |
| Logic Family | — | CMOS, TTL-compatible I/O |
| Programmable Pins | — | 16 bidirectional I/O + 4 dedicated input = 20 |
| Total Package Pins | — | 28 |
| Erasure Method | — | UV light through ceramic quartz window |
| Lead-Free | — | unknown |