EPM5016DC-15 vs EPM5032DC-2 Vergleich

Detaillierter Direktvergleich von EPM5016DC-15 von Altera und EPM5032DC-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5016DC-15 EPM5032DC-2
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $10,75 $8,75
Device Family MAX 5000 —
Product Type EPLD (Erasable Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 16 32
Logic Array Blocks (LABs) 2 4
Dedicated Inputs 4 —
User I/O Pins 12 —
Pin-to-Pin Delay (tpd) 15 ns —
Maximum Frequency (fmax) 71 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V 5 V (single supply, +/-5%)
Programming Voltage (VPP) 12.75 V —
Betriebstemperatur 0 °C to 70 °C (commercial) 0C to +70C (commercial grade)
Gehäuse Ceramic DIP-24 (windowed) 20-pin CDIP (Ceramic DIP)
Montageart Through-Hole Through-Hole (DIP)
Process Technology CMOS EPROM —
Configuration Memory Non-volatile UV-erasable EPROM EPROM (one-time programmable per generation; UV-erasable variants exist)
RoHS-Status [DATA_NEEDED: RoHS status - pre-RoHS era part, likely non-compliant] [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS]
Lead Finish [DATA_NEEDED: lead-free status] —
Series — MAX 5000
Usable Gates (typical) — 600
Speed Grade — -2 (tPD ~25 ns, commercial)
Programmable Pins / I/O — 20 pins (JEDEC-standard 0.300" ceramic DIP)
Programming Interface — Altera ByteBlaster / parallel-port JTAG-style ISP
Interconnect — Programmable Interconnect Array (PIA) with deterministic timing
MSL-Level — Not applicable (through-hole hermetic ceramic)

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