EPM5016DC-17 vs EPM5032DC-2 Vergleich

Detaillierter Direktvergleich von EPM5016DC-17 von Altera und EPM5032DC-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5016DC-17 EPM5032DC-2
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $16,20 $8,75
Family MAX 5000 —
Macrocells 16 32
Logic Elements [DATA_NEEDED: LE count for MAX 5000 family] —
User I/O Pins (max) 24 —
Propagation Delay (tPD) 17 ns —
Counter Frequency (fCNT) 67 MHz —
Supply Voltage (VCC) 5 V 5 V (single supply, +/-5%)
I/O Standard TTL-compatible —
Process Technology 0.75 micron CMOS EEPROM —
Gehäuse Ceramic DIP-24 (DC suffix) 20-pin CDIP (Ceramic DIP)
Pin-Anzahl 24 —
Montageart Through-hole Through-Hole (DIP)
Betriebstemperatur 0C to +70C (commercial) 0C to +70C (commercial grade)
In-System Programmability Yes (ByteBlaster / BitBlaster) —
Configuration Memory On-chip EEPROM (non-volatile) EPROM (one-time programmable per generation; UV-erasable variants exist)
RoHS-Status [DATA_NEEDED: confirmed compliance status from manufacturer] [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS]
Product Type — CPLD (Complex Programmable Logic Device)
Series — MAX 5000
Usable Gates (typical) — 600
Logic Array Blocks (LABs) — 4
Speed Grade — -2 (tPD ~25 ns, commercial)
Programmable Pins / I/O — 20 pins (JEDEC-standard 0.300" ceramic DIP)
Programming Interface — Altera ByteBlaster / parallel-port JTAG-style ISP
Interconnect — Programmable Interconnect Array (PIA) with deterministic timing
MSL-Level — Not applicable (through-hole hermetic ceramic)

Datenblätter & Ressourcen

Alle Produkte durchsuchen BOM erstellen Angebot anfordern