EPM5016LC-17 vs EPM5016PC-1 Vergleich
Detaillierter Direktvergleich von EPM5016LC-17 von Altera und EPM5016PC-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5016LC-17 | EPM5016PC-1 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,95 | $9,95 |
| Family | MAX 5000 EPLD | MAX 5000 EPLD |
| Technology | CMOS, UV-erasable | — |
| Macrocells | 16 | 16 |
| Product Terms | 160 | — |
| Dedicated Inputs | 7 | — |
| I/O Pins | 8 | — |
| Total Input Pins | 16 | — |
| Outputs | 8 | — |
| External Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 17 ns | 35 ns |
| Architecture | PAL-type with Programmable Interconnect Array (PIA) | — |
| Gehäuse | Windowed Ceramic DIP (LC) | PDIP-20 (plastic DIP, through-hole) |
| Versorgungsspannung | [DATA_NEEDED: VCC range] | — |
| Betriebstemperatur | [DATA_NEEDED: temperature grade] | 0 C to +70 C (commercial) |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | Non-compliant (PDIP with SnPb leads, pre-RoHS era) |
| Logic Compatibility | TTL/CMOS | — |
| Usable Gates | — | 200 |
| Logic Array Blocks (LABs) | — | 1 |
| Maximum Frequency (fMAX) | — | 62 MHz |
| Setup Time (tSU) | — | [DATA_NEEDED: setup time ns] |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Supply Current (ICC) | — | 50 mA typical |
| Pin-Anzahl | — | 20 |
| Configuration Memory | — | CMOS EEPROM (UV-erasable) |
| Programming Interface | — | Altera 4-pin JTAG-style (MasterBlaster / ByteBlaster) |