EPM5032PC-15 vs EPM5032LC-20 Vergleich
Detaillierter Direktvergleich von EPM5032PC-15 von Altera und EPM5032LC-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5032PC-15 | EPM5032LC-20 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,10 | $8,40 |
| Device Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable PLD) | — |
| Macro Cells | 32 | — |
| Usable Gates | 600 | 600 gates |
| Logic Elements / LABs | 1 LAB (4 macrocells per group) | — |
| Propagation Delay (tPD) | 15 ns | 20 ns |
| Maximum Internal Frequency | 76.9 MHz (some sources list 83.3 MHz) | — |
| Operating Voltage (VCC) | 5 V (typ.) | — |
| Technology Node | 0.8 micron CMOS | — |
| Configuration Memory | UV-Erasable EPROM | — |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | 16 |
| Total Array Inputs | 24 | — |
| Gehäuse | 28-pin PDIP (PC suffix = windowed CerDIP) | LCC-28 (Plastic Leaded Chip Carrier, J-lead) |
| Pin/Package Suffix | PC = Windowed Ceramic DIP | — |
| Speed Grade | 15 (15 ns tPD) | -20 (20 ns pin-to-pin) |
| Betriebstemperatur | 0C to +70C (commercial) | 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants) |
| Programming Tool | Altera Logic Programmer + MAX+plus II | — |
| RoHS-Status | Non-compliant (CerDIP window, contains Be) | [DATA_NEEDED: RoHS status] |
| Lead-Free | No | — |
| Montageart | Through-Hole (DIP) | Surface Mount |
| Product Type | — | EPLD / CPLD (One-Time Programmable / UV-Erasable) |
| Macrocells | — | 32 |
| Logic Blocks (LABs) | — | 1 |
| Maximum Frequency | — | 71.4 MHz |
| Supply Voltage (VCC) | — | 5 V ±5% |
| Total Inputs | — | 24 |
| Output Functions | — | 16 |
| Product Terms per Output | — | 16 |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |
| MSL-Level | — | [DATA_NEEDED: MSL] |