EPM5064JC vs EPM5128GC Vergleich
Detaillierter Direktvergleich von EPM5064JC von Altera und EPM5128GC von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5064JC | EPM5128GC |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,10 | $19,20 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable PLD) | — |
| Macrocells | 64 | 128 |
| Usable Gates | 1,250 (approx.) | 2,500 |
| Logic Array Inputs | 36 | — |
| Logic Array Outputs | 64 | — |
| Gehäuse | 68-pin PLCC (JEDEC) | — |
| Montageart | Surface Mount (socketed) | Through-Hole (PGA socket required) |
| Supply Voltage (VCC) | 5 V (typical, 4.75 V - 5.25 V range) | — |
| I/O Logic Level | TTL / CMOS compatible | — |
| Configuration Memory | EPROM (UV-erasable window or OTP) | Non-volatile UV-EPROM (windowed ceramic) |
| Betriebstemperatur | [DATA_NEEDED: operating temperature grade] | — |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: specific tPD grade value] | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fCNT grade value] | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL-Level | [DATA_NEEDED: MSL rating] | — |
| Programming Tool | Altera MAX+PLUS II / Quartus II (legacy device support) | — |
| Logic Elements / LABs | — | [DATA_NEEDED: LAB count] |
| User I/Os | — | 68 |
| Package Type | — | WPGA (Windowed Ceramic Pin Grid Array) |
| Package Code | — | WPGA |
| Number of Terminals | — | 68 |
| Terminal Form | — | PIN/PEG (through-hole PGA with alignment pegs) |
| Package Shape | — | Square |
| Temperature Grade | — | Commercial |
| Supply Voltage (Vcc) | — | 5 V |
| Process Technology | — | CMOS, UV-erasable |
| Architecture | — | EPLD, programmable AND/OR array with fixed OR plane |
| Propagation Delay (tpd) | — | [DATA_NEEDED: tpd in ns] |
| Maximum Frequency (fmax) | — | [DATA_NEEDED: fmax in MHz] |
| Programmable Security Bit | — | Yes |