EPM5064JC vs EPM5128GC Comparison
Detailed side-by-side comparison of EPM5064JC by Altera and EPM5128GC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5064JC | EPM5128GC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.10 | $19.20 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable PLD) | β |
| Macrocells | 64 | 128 |
| Usable Gates | 1,250 (approx.) | 2,500 |
| Logic Array Inputs | 36 | β |
| Logic Array Outputs | 64 | β |
| Package | 68-pin PLCC (JEDEC) | β |
| Mounting Type | Surface Mount (socketed) | Through-Hole (PGA socket required) |
| Supply Voltage (VCC) | 5 V (typical, 4.75 V - 5.25 V range) | β |
| I/O Logic Level | TTL / CMOS compatible | β |
| Configuration Memory | EPROM (UV-erasable window or OTP) | Non-volatile UV-EPROM (windowed ceramic) |
| Operating Temperature | [DATA_NEEDED: operating temperature grade] | β |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: specific tPD grade value] | β |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fCNT grade value] | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| MSL Level | [DATA_NEEDED: MSL rating] | β |
| Programming Tool | Altera MAX+PLUS II / Quartus II (legacy device support) | β |
| Logic Elements / LABs | β | [DATA_NEEDED: LAB count] |
| User I/Os | β | 68 |
| Package Type | β | WPGA (Windowed Ceramic Pin Grid Array) |
| Package Code | β | WPGA |
| Number of Terminals | β | 68 |
| Terminal Form | β | PIN/PEG (through-hole PGA with alignment pegs) |
| Package Shape | β | Square |
| Temperature Grade | β | Commercial |
| Supply Voltage (Vcc) | β | 5 V |
| Process Technology | β | CMOS, UV-erasable |
| Architecture | β | EPLD, programmable AND/OR array with fixed OR plane |
| Propagation Delay (tpd) | β | [DATA_NEEDED: tpd in ns] |
| Maximum Frequency (fmax) | β | [DATA_NEEDED: fmax in MHz] |
| Programmable Security Bit | β | Yes |