EPM5064LC-2 vs EPM5064LC Vergleich
Detaillierter Direktvergleich von EPM5064LC-2 von Altera und EPM5064LC von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5064LC-2 | EPM5064LC |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,40 | $7,10 |
| Device Family | MAX 5000 | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 64 | — |
| Logic Array Blocks (LABs) | 4 | 4 |
| Logic Elements per LAB | 16 | — |
| Number of Inputs | 36 (7 dedicated + 28 I/O) | — |
| Number of I/O Pins | 28 | — |
| Number of Flip-Flops | 28 | — |
| Propagation Delay (tPD) | 45 ns | 55 ns |
| Maximum Internal Frequency | 40 MHz | — |
| Process Technology | CMOS, OTP EPROM (UV-erasable base) | CMOS EPROM |
| Programmable Polarity | Yes | — |
| Programmable Output Enable | Yes, per macrocell | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V |
| Betriebstemperatur | -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source] | 0C to +70C (Commercial) |
| Gehäuse | PLCC-44 (J-Lead, plastic) | PLCC-44 (LCC-44, J-lead) |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: not specified in source] | [DATA_NEEDED: RoHS status - pre-RoHS legacy part, likely non_compliant] |
| Programming Method | Altera byte-wide / JTAG programmer | — |
| Family | — | MAX 5000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Programming Type | — | OTP (One-Time-Programmable, UV-erasable EPROM) |
| Macro Cells | — | 64 |
| Usable Gates | — | 1.25K |
| Total Inputs | — | 36 (7 dedicated + 29 I/O) |
| I/O Pins | — | 28 bidirectional + 4 dedicated input |
| Lead Free | — | [DATA_NEEDED: lead-free status] |