EPM5128GC-1 vs EPM5128GC-2 Vergleich
Detaillierter Direktvergleich von EPM5128GC-1 von Altera und EPM5128GC-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5128GC-1 | EPM5128GC-2 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $18,95 | $8,95 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-erasable CMOS CPLD | — |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | — |
| Dedicated Inputs | 7 | — |
| Maximum User I/O Pins | 52 | — |
| Nominal Supply Voltage | 5 V | — |
| Supply Voltage Range | 4.75 V to 5.25 V | — |
| Maximum Operating Frequency | 62.5 MHz | 50 MHz |
| Propagation Delay (tPD) | 16 ns (typical, -1 speed grade) | Approx. 25 ns (typical, -2 speed grade) |
| Gehäuse | PGA-96+ (Pin Grid Array, ceramic windowed) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Betriebstemperatur | -40C to +85C (industrial) | 0C to +70C (commercial) |
| IOL / IOH | 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec]) | — |
| Security Bit | Programmable, prevents readback | — |
| Programming Method | UV erase + EPROM program (or device programmer) | — |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy] | — |
| Logic Elements / Gates | — | 2,500 usable gates |
| Number of Usable Gates | — | 2,500 |
| Supply Voltage (VCC) | — | 5 V (nominal) |
| Package Type | — | 68-pin PGA (Pin Grid Array) |
| Package Code (per Partstack) | — | WPGA |
| Number of Terminals | — | 68 |
| Programming Technology | — | UV-erasable EPROM |
| Grade (per Partstack) | — | COMMERCIAL |
| Terminal Form | — | PIN/PEG |
| Configuration Memory | — | Non-volatile, one-time programmable (erasable via UV) |