EPM5128GC2 vs EPM5128GC-1 Vergleich

Detaillierter Direktvergleich von EPM5128GC2 von Altera und EPM5128GC-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5128GC2 EPM5128GC-1
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $54,00 $18,95
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable Programmable Logic Device) UV-erasable CMOS CPLD
Macro Cells 128 —
Usable Gates 2.5K 2,500
Logic Array Blocks (LABs) 8 (16 macro cells each) —
Maximum Internal Frequency 50 MHz —
Supply Voltage VCC 5 V —
I/O Pins 64 —
Dedicated Inputs 16 7
Gehäuse Ceramic PGA (GC, windowed) PGA-96+ (Pin Grid Array, ceramic windowed)
Programmable Flip-Flop Modes D / T / JK / SR (selectable) —
Architecture AND/OR plane + programmable macro cell + PIA —
Process Technology CMOS EPROM —
Reprogrammability UV-erasable (windowed ceramic package) —
Betriebstemperatur [DATA_NEEDED: operating temperature range] -40C to +85C (industrial)
RoHS-Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy]
Configuration Memory On-chip EPROM (no external boot device) —
Pin-Anzahl [DATA_NEEDED: total PGA pin count] —
Macrocells — 128
Maximum User I/O Pins — 52
Nominal Supply Voltage — 5 V
Supply Voltage Range — 4.75 V to 5.25 V
Maximum Operating Frequency — 62.5 MHz
Propagation Delay (tPD) — 16 ns (typical, -1 speed grade)
Technology — CMOS, UV-erasable EPROM
IOL / IOH — 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec])
Security Bit — Programmable, prevents readback
Programming Method — UV erase + EPROM program (or device programmer)
MSL-Level — [DATA_NEEDED: MSL level]

Datenblätter & Ressourcen

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