EPM5128GC2 vs EPM5128GC-1 비교
다음의 상세 나란히 비교: EPM5128GC2 제조: Altera 및 EPM5128GC-1 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5128GC2 | EPM5128GC-1 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $54.00 | $18.95 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV-erasable CMOS CPLD |
| Macro Cells | 128 | — |
| Usable Gates | 2.5K | 2,500 |
| Logic Array Blocks (LABs) | 8 (16 macro cells each) | — |
| Maximum Internal Frequency | 50 MHz | — |
| Supply Voltage VCC | 5 V | — |
| I/O Pins | 64 | — |
| Dedicated Inputs | 16 | 7 |
| 패키지 | Ceramic PGA (GC, windowed) | PGA-96+ (Pin Grid Array, ceramic windowed) |
| Programmable Flip-Flop Modes | D / T / JK / SR (selectable) | — |
| Architecture | AND/OR plane + programmable macro cell + PIA | — |
| Process Technology | CMOS EPROM | — |
| Reprogrammability | UV-erasable (windowed ceramic package) | — |
| 동작 온도 | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) |
| RoHS 상태 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy] |
| Configuration Memory | On-chip EPROM (no external boot device) | — |
| 핀 수 | [DATA_NEEDED: total PGA pin count] | — |
| Macrocells | — | 128 |
| Maximum User I/O Pins | — | 52 |
| Nominal Supply Voltage | — | 5 V |
| Supply Voltage Range | — | 4.75 V to 5.25 V |
| Maximum Operating Frequency | — | 62.5 MHz |
| Propagation Delay (tPD) | — | 16 ns (typical, -1 speed grade) |
| Technology | — | CMOS, UV-erasable EPROM |
| IOL / IOH | — | 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec]) |
| Security Bit | — | Programmable, prevents readback |
| Programming Method | — | UV erase + EPROM program (or device programmer) |
| MSL 레벨 | — | [DATA_NEEDED: MSL level] |