EPM5128JC-2 vs EPM5128GC Vergleich

Detaillierter Direktvergleich von EPM5128JC-2 von Altera und EPM5128GC von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5128JC-2 EPM5128GC
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $21,75 $19,20
Family MAX 5000 MAX 5000
Device Type UV-Erasable Programmable Logic Device (PLD) —
Macrocells 128 128
Dedicated Inputs 7 —
Propagation Delay (tPD) 45 ns (max) —
Maximum Counter Frequency (fCNT) 50 MHz —
Input Setup Time (tSU) 7.5 ns —
Output Drive Current (IOH/IOL) 12 mA DC —
Process Technology CMOS CMOS, UV-erasable
Gehäuse 68-pin CQCC (Ceramic Quad Flat Pack), windowed —
Montageart Surface Mount Through-Hole (PGA socket required)
Betriebstemperatur [DATA_NEEDED: operating temperature range] —
Versorgungsspannung 5 V (nominal) —
Program/Erase Method UV (ceramic window) —
Erase/Program Cycles [DATA_NEEDED: minimum erase/program cycles] —
RoHS-Status Non-compliant (ceramic windowed package contains lead-bearing solder) [DATA_NEEDED: RoHS compliance]
Logic Family TTL-compatible I/O —
Usable Gates — 2,500
Logic Elements / LABs — [DATA_NEEDED: LAB count]
User I/Os — 68
Package Type — WPGA (Windowed Ceramic Pin Grid Array)
Package Code — WPGA
Number of Terminals — 68
Terminal Form — PIN/PEG (through-hole PGA with alignment pegs)
Package Shape — Square
Temperature Grade — Commercial
Supply Voltage (Vcc) — 5 V
Architecture — EPLD, programmable AND/OR array with fixed OR plane
Propagation Delay (tpd) — [DATA_NEEDED: tpd in ns]
Maximum Frequency (fmax) — [DATA_NEEDED: fmax in MHz]
Programmable Security Bit — Yes
Configuration Memory — Non-volatile UV-EPROM (windowed ceramic)

Datenblätter & Ressourcen

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