EPM5128JC-2 vs EPM5128GC-1 Vergleich

Detaillierter Direktvergleich von EPM5128JC-2 von Altera und EPM5128GC-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5128JC-2 EPM5128GC-1
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $21,75 $18,95
Family MAX 5000 MAX 5000
Device Type UV-Erasable Programmable Logic Device (PLD) UV-erasable CMOS CPLD
Macrocells 128 128
Dedicated Inputs 7 7
Propagation Delay (tPD) 45 ns (max) 16 ns (typical, -1 speed grade)
Maximum Counter Frequency (fCNT) 50 MHz —
Input Setup Time (tSU) 7.5 ns —
Output Drive Current (IOH/IOL) 12 mA DC —
Process Technology CMOS —
Gehäuse 68-pin CQCC (Ceramic Quad Flat Pack), windowed PGA-96+ (Pin Grid Array, ceramic windowed)
Montageart Surface Mount —
Betriebstemperatur [DATA_NEEDED: operating temperature range] -40C to +85C (industrial)
Versorgungsspannung 5 V (nominal) —
Program/Erase Method UV (ceramic window) —
Erase/Program Cycles [DATA_NEEDED: minimum erase/program cycles] —
RoHS-Status Non-compliant (ceramic windowed package contains lead-bearing solder) [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy]
Logic Family TTL-compatible I/O —
Usable Gates — 2,500
Maximum User I/O Pins — 52
Nominal Supply Voltage — 5 V
Supply Voltage Range — 4.75 V to 5.25 V
Maximum Operating Frequency — 62.5 MHz
Technology — CMOS, UV-erasable EPROM
IOL / IOH — 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec])
Security Bit — Programmable, prevents readback
Programming Method — UV erase + EPROM program (or device programmer)
MSL-Level — [DATA_NEEDED: MSL level]

Datenblätter & Ressourcen

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