EPM5128JC-2 vs EPM5128GC-1 对比
详细并排对比 EPM5128JC-2 出自 Altera 和 EPM5128GC-1 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5128JC-2 | EPM5128GC-1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $21.75 | $18.95 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable Programmable Logic Device (PLD) | UV-erasable CMOS CPLD |
| Macrocells | 128 | 128 |
| Dedicated Inputs | 7 | 7 |
| Propagation Delay (tPD) | 45 ns (max) | 16 ns (typical, -1 speed grade) |
| Maximum Counter Frequency (fCNT) | 50 MHz | — |
| Input Setup Time (tSU) | 7.5 ns | — |
| Output Drive Current (IOH/IOL) | 12 mA DC | — |
| Process Technology | CMOS | — |
| 封装 | 68-pin CQCC (Ceramic Quad Flat Pack), windowed | PGA-96+ (Pin Grid Array, ceramic windowed) |
| 安装类型 | Surface Mount | — |
| 工作温度 | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) |
| 电源电压 | 5 V (nominal) | — |
| Program/Erase Method | UV (ceramic window) | — |
| Erase/Program Cycles | [DATA_NEEDED: minimum erase/program cycles] | — |
| RoHS 状态 | Non-compliant (ceramic windowed package contains lead-bearing solder) | [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy] |
| Logic Family | TTL-compatible I/O | — |
| Usable Gates | — | 2,500 |
| Maximum User I/O Pins | — | 52 |
| Nominal Supply Voltage | — | 5 V |
| Supply Voltage Range | — | 4.75 V to 5.25 V |
| Maximum Operating Frequency | — | 62.5 MHz |
| Technology | — | CMOS, UV-erasable EPROM |
| IOL / IOH | — | 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec]) |
| Security Bit | — | Programmable, prevents readback |
| Programming Method | — | UV erase + EPROM program (or device programmer) |
| MSL 等级 | — | [DATA_NEEDED: MSL level] |