EPM5128JC-2 vs EPM5128JC-1 Vergleich

Detaillierter Direktvergleich von EPM5128JC-2 von Altera und EPM5128JC-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5128JC-2 EPM5128JC-1
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $21,75 $24,95
Family MAX 5000 MAX 5000
Device Type UV-Erasable Programmable Logic Device (PLD) Erasable Programmable Logic Device (EPLD/CPLD)
Macrocells 128 128
Dedicated Inputs 7 —
Propagation Delay (tPD) 45 ns (max) —
Maximum Counter Frequency (fCNT) 50 MHz —
Input Setup Time (tSU) 7.5 ns —
Output Drive Current (IOH/IOL) 12 mA DC —
Process Technology CMOS —
Gehäuse 68-pin CQCC (Ceramic Quad Flat Pack), windowed 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier)
Montageart Surface Mount Surface Mount
Betriebstemperatur [DATA_NEEDED: operating temperature range] [DATA_NEEDED: temperature grade]
Versorgungsspannung 5 V (nominal) —
Program/Erase Method UV (ceramic window) —
Erase/Program Cycles [DATA_NEEDED: minimum erase/program cycles] —
RoHS-Status Non-compliant (ceramic windowed package contains lead-bearing solder) non_compliant (ceramic windowed package)
Logic Family TTL-compatible I/O —
Usable Gates — 2,500
Logic Array Blocks (LABs) — [DATA_NEEDED: LAB count]
Maximum Operating Frequency — 62.5 MHz
Pin-to-Pin Propagation Delay (tPD) — 40 ns
Supply Voltage (VCC) — 4.75 V to 5.25 V (5 V nominal)
Technology — CMOS, UV-erasable EPROM
Programming Interface — JTAG / Altera dedicated programmer
Configuration Memory — Non-volatile EPROM (UV-erasable)
Lebenszyklusstatus — Obsolete - last-time-buy inventory only

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