EPM5128JC-2 vs EPM5128LC-1 Vergleich

Detaillierter Direktvergleich von EPM5128JC-2 von Altera und EPM5128LC-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5128JC-2 EPM5128LC-1
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $21,75 $8,20
Family MAX 5000 MAX 5000
Device Type UV-Erasable Programmable Logic Device (PLD) —
Macrocells 128 —
Dedicated Inputs 7 7
Propagation Delay (tPD) 45 ns (max) —
Maximum Counter Frequency (fCNT) 50 MHz —
Input Setup Time (tSU) 7.5 ns —
Output Drive Current (IOH/IOL) 12 mA DC —
Process Technology CMOS CMOS EPROM, UV-erasable
Gehäuse 68-pin CQCC (Ceramic Quad Flat Pack), windowed —
Montageart Surface Mount Surface Mount (J-lead PLCC socket compatible)
Betriebstemperatur [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
Versorgungsspannung 5 V (nominal) —
Program/Erase Method UV (ceramic window) —
Erase/Program Cycles [DATA_NEEDED: minimum erase/program cycles] —
RoHS-Status Non-compliant (ceramic windowed package contains lead-bearing solder) [DATA_NEEDED: RoHS status]
Logic Family TTL-compatible I/O —
Logic Elements / Macrocells — 128 macrocells
Number of Usable Gates — [DATA_NEEDED: usable gates]
Bidirectional I/O Pins — 52
Total User I/O — 60 (max)
Propagation Delay (tpd) — 30 ns
Supply Voltage (VCC) — 5 V (±10%)
Programmability — UV-erasable / OTP (windowed package)
Package Type — 68-pin J-lead ceramic chip carrier (PLCC windowed)
JTAG Support — IEEE 1149.1 boundary-scan
Lead-Free — [DATA_NEEDED: lead-free status]

Datenblätter & Ressourcen

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