EPM5128JC-2 vs EPM5128LC-1 Comparison
Detailed side-by-side comparison of EPM5128JC-2 by Altera and EPM5128LC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5128JC-2 | EPM5128LC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $21.75 | $8.20 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable Programmable Logic Device (PLD) | β |
| Macrocells | 128 | β |
| Dedicated Inputs | 7 | 7 |
| Propagation Delay (tPD) | 45 ns (max) | β |
| Maximum Counter Frequency (fCNT) | 50 MHz | β |
| Input Setup Time (tSU) | 7.5 ns | β |
| Output Drive Current (IOH/IOL) | 12 mA DC | β |
| Process Technology | CMOS | CMOS EPROM, UV-erasable |
| Package | 68-pin CQCC (Ceramic Quad Flat Pack), windowed | β |
| Mounting Type | Surface Mount | Surface Mount (J-lead PLCC socket compatible) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Supply Voltage | 5 V (nominal) | β |
| Program/Erase Method | UV (ceramic window) | β |
| Erase/Program Cycles | [DATA_NEEDED: minimum erase/program cycles] | β |
| RoHS Status | Non-compliant (ceramic windowed package contains lead-bearing solder) | [DATA_NEEDED: RoHS status] |
| Logic Family | TTL-compatible I/O | β |
| Logic Elements / Macrocells | β | 128 macrocells |
| Number of Usable Gates | β | [DATA_NEEDED: usable gates] |
| Bidirectional I/O Pins | β | 52 |
| Total User I/O | β | 60 (max) |
| Propagation Delay (tpd) | β | 30 ns |
| Supply Voltage (VCC) | β | 5 V (Β±10%) |
| Programmability | β | UV-erasable / OTP (windowed package) |
| Package Type | β | 68-pin J-lead ceramic chip carrier (PLCC windowed) |
| JTAG Support | β | IEEE 1149.1 boundary-scan |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |