EPM5128JC-2 vs EPM5128LC2 Vergleich
Detaillierter Direktvergleich von EPM5128JC-2 von Altera und EPM5128LC2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM5128LC2 - 128-Macrocell MAX 5000 CPLD, 45ns, 5V | Altera
EPM5128LC2 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM5128JC-2 | EPM5128LC2 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $21,75 | $22,40 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable Programmable Logic Device (PLD) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | 128 |
| Dedicated Inputs | 7 | — |
| Propagation Delay (tPD) | 45 ns (max) | 45 ns |
| Maximum Counter Frequency (fCNT) | 50 MHz | — |
| Input Setup Time (tSU) | 7.5 ns | — |
| Output Drive Current (IOH/IOL) | 12 mA DC | — |
| Process Technology | CMOS | CMOS EPROM |
| Gehäuse | 68-pin CQCC (Ceramic Quad Flat Pack), windowed | PGA (Pin Grid Array, ceramic) |
| Montageart | Surface Mount | Through-Hole / Socketed |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (extended commercial) |
| Versorgungsspannung | 5 V (nominal) | — |
| Program/Erase Method | UV (ceramic window) | — |
| Erase/Program Cycles | [DATA_NEEDED: minimum erase/program cycles] | — |
| RoHS-Status | Non-compliant (ceramic windowed package contains lead-bearing solder) | [DATA_NEEDED: RoHS status] |
| Logic Family | TTL-compatible I/O | — |
| Logic Array Blocks (LABs) | — | 8 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Global Clock Inputs | — | 1 dedicated |
| Supply Voltage (VCC) | — | 5 V |
| Configuration Memory | — | On-chip EPROM (non-volatile) |
| Boundary Scan | — | JTAG / IEEE 1149.1 |