EPM5128JC-2 vs EPM5128LC2 比較
詳細な並列比較: EPM5128JC-2 メーカー: Altera および EPM5128LC2 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5128JC-2 | EPM5128LC2 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $21.75 | $22.40 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable Programmable Logic Device (PLD) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | 128 |
| Dedicated Inputs | 7 | — |
| Propagation Delay (tPD) | 45 ns (max) | 45 ns |
| Maximum Counter Frequency (fCNT) | 50 MHz | — |
| Input Setup Time (tSU) | 7.5 ns | — |
| Output Drive Current (IOH/IOL) | 12 mA DC | — |
| Process Technology | CMOS | CMOS EPROM |
| パッケージ | 68-pin CQCC (Ceramic Quad Flat Pack), windowed | PGA (Pin Grid Array, ceramic) |
| 実装タイプ | Surface Mount | Through-Hole / Socketed |
| 動作温度 | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (extended commercial) |
| 電源電圧 | 5 V (nominal) | — |
| Program/Erase Method | UV (ceramic window) | — |
| Erase/Program Cycles | [DATA_NEEDED: minimum erase/program cycles] | — |
| RoHS ステータス | Non-compliant (ceramic windowed package contains lead-bearing solder) | [DATA_NEEDED: RoHS status] |
| Logic Family | TTL-compatible I/O | — |
| Logic Array Blocks (LABs) | — | 8 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Global Clock Inputs | — | 1 dedicated |
| Supply Voltage (VCC) | — | 5 V |
| Configuration Memory | — | On-chip EPROM (non-volatile) |
| Boundary Scan | — | JTAG / IEEE 1149.1 |