EPM5192AGC-15 vs EPM5192AGC84-20 Vergleich
Detaillierter Direktvergleich von EPM5192AGC-15 von Altera und EPM5192AGC84-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192AGC-15 | EPM5192AGC84-20 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $27,80 | $41,20 |
| Product Type | EPLD (Erasable Programmable Logic Device) | Complex Programmable Logic Device (CPLD) |
| Series | MAX 5000 | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks | 16 (typical for 192-macrocell MAX 5000) | — |
| Maximum User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Total Inputs | 72 | — |
| Propagation Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | — |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Gehäuse | Ceramic Pin Grid Array (PGA) | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) |
| Programming Method | UV erase + EPROM program (via Altera programmer) | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | — |
| RoHS-Status | [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] | [DATA_NEEDED: RoHS compliance] |
| Lebenszyklusstatus | Obsolete / Last Time Buy (per Altera legacy product list) | — |
| Family | — | MAX 5000 |
| User I/O Pins | — | 64 |
| Logic Gates (typical) | — | [DATA_NEEDED: typical gate count] |
| Maximum Clock Frequency (fMAX) | — | 66.7 MHz |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Speed Grade | — | -20 |
| Package Code | — | WPGA |
| Erasure Method | — | UV-Erasable (with OTP window) |
| Process Technology | — | CMOS |
| Operating Temperature Grade | — | Commercial |
| Versorgungsspannung | — | [DATA_NEEDED: VCC range] |
| I/O Standard | — | 5V CMOS / TTL compatible |
| Montageart | — | Through-Hole (Pin Grid Array socket) |