EPM5192AGC-15 vs EPM5192AGC84-20 对比
详细并排对比 EPM5192AGC-15 出自 Altera 和 EPM5192AGC84-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5192AGC-15 | EPM5192AGC84-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $27.80 | $41.20 |
| Product Type | EPLD (Erasable Programmable Logic Device) | Complex Programmable Logic Device (CPLD) |
| Series | MAX 5000 | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks | 16 (typical for 192-macrocell MAX 5000) | — |
| Maximum User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Total Inputs | 72 | — |
| Propagation Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | — |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS, UV-erasable EPROM | — |
| 封装 | Ceramic Pin Grid Array (PGA) | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) |
| Programming Method | UV erase + EPROM program (via Altera programmer) | — |
| 工作温度 | [DATA_NEEDED: operating temperature range] | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] | [DATA_NEEDED: RoHS compliance] |
| 生命周期状态 | Obsolete / Last Time Buy (per Altera legacy product list) | — |
| Family | — | MAX 5000 |
| User I/O Pins | — | 64 |
| Logic Gates (typical) | — | [DATA_NEEDED: typical gate count] |
| Maximum Clock Frequency (fMAX) | — | 66.7 MHz |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Speed Grade | — | -20 |
| Package Code | — | WPGA |
| Erasure Method | — | UV-Erasable (with OTP window) |
| Process Technology | — | CMOS |
| Operating Temperature Grade | — | Commercial |
| 电源电压 | — | [DATA_NEEDED: VCC range] |
| I/O Standard | — | 5V CMOS / TTL compatible |
| 安装类型 | — | Through-Hole (Pin Grid Array socket) |