EPM5192AGC-15 vs EPM5192AJC-25 Vergleich
Detaillierter Direktvergleich von EPM5192AGC-15 von Altera und EPM5192AJC-25 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192AGC-15 | EPM5192AJC-25 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $27,80 | $8,20 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Series | MAX 5000 | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks | 16 (typical for 192-macrocell MAX 5000) | — |
| Maximum User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Total Inputs | 72 | — |
| Propagation Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | 25 ns |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Gehäuse | Ceramic Pin Grid Array (PGA) | PLCC-68 (windowed ceramic, AJC) |
| Programming Method | UV erase + EPROM program (via Altera programmer) | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: exact operating temperature range] |
| RoHS-Status | [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] | [DATA_NEEDED: RoHS compliance status] |
| Lebenszyklusstatus | Obsolete / Last Time Buy (per Altera legacy product list) | — |
| Family | — | MAX 5000 EPLD |
| Manufacturer | — | Altera (now Intel PSG) |
| Pin-Anzahl | — | 68 |
| Montageart | — | Surface Mount |
| Versorgungsspannung | — | 5 V (typical) |
| Logic Blocks | — | MAX 5000 LABs (Logic Array Blocks) |
| Programmable Pins | — | [DATA_NEEDED: number of user I/O pins] |
| Erasure Method | — | UV-erasable (windowed ceramic package) |
| Programming Technology | — | EPROM (non-volatile) |
| Military Grade | — | Likely MIL-STD-883 processing per 'J' suffix in AJC marking (verify) |