EPM5192AGC vs EPM5192AQC-1 Vergleich

Detaillierter Direktvergleich von EPM5192AGC von Altera und EPM5192AQC-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192AGC EPM5192AQC-1
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $56,00 $17,40
Family MAX 5000 (High-Speed, High-Density MAX 5000 Devices) MAX 5000
Device Type UV-Erasable / OTP Complex PLD (EPLD) One-Time Programmable (OTP) CPLD
Macrocells 192 192
Logic Density High-density (per MAX 5000 family definition) —
Architecture CMOS, sum-of-products with macrocell output logic —
Process Technology CMOS —
Gehäuse 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) PQFP-100 (Plastic Quad Flat Pack)
Speed Grade Suffix C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) —
Betriebstemperatur [DATA_NEEDED: operating temperature range] —
Programmability UV-erasable (windowed package) / One-Time-Programmable (windowless variant) —
Security Bit Programmable security bit (per MAX 5000 family) —
Versorgungsspannung [DATA_NEEDED: VCC nominal and tolerance] —
Montageart Through-hole (Pin Grid Array) Surface Mount
RoHS-Status Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) [DATA_NEEDED: RoHS status]
Lifecycle Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) —
Programming Support MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers —
Logic Elements / Logic Array Blocks — [DATA_NEEDED: number of LABs]
Propagation Delay (tPD) — 40 ns
Maximum Operating Frequency — [DATA_NEEDED: fMAX value]
User I/O Pins — 64
Dedicated Inputs — 7
Total Inputs / Outputs — 72 inputs / 64 outputs
Supply Voltage (VCC) — 4.75 V to 5.25 V
Nominal Supply Voltage — 5 V
Betriebstemperaturbereich — 0 °C to +70 °C (commercial)
Terminal Pitch — 0.635 mm
Technology — CMOS, UV-Erasable / OTP EPROM
Configuration Method — One-Time Programmable (OTP) / UV-Erasable
Lead-Free — [DATA_NEEDED: lead-free status]

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