EPM5192AGC vs EPM5192AQC-1 Comparaison
Comparaison détaillée côte à côte de EPM5192AGC par Altera et EPM5192AQC-1 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192AGC | EPM5192AQC-1 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $56,00 | $17,40 |
| Family | MAX 5000 (High-Speed, High-Density MAX 5000 Devices) | MAX 5000 |
| Device Type | UV-Erasable / OTP Complex PLD (EPLD) | One-Time Programmable (OTP) CPLD |
| Macrocells | 192 | 192 |
| Logic Density | High-density (per MAX 5000 family definition) | — |
| Architecture | CMOS, sum-of-products with macrocell output logic | — |
| Process Technology | CMOS | — |
| Boîtier | 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) | PQFP-100 (Plastic Quad Flat Pack) |
| Speed Grade Suffix | C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | — |
| Programmability | UV-erasable (windowed package) / One-Time-Programmable (windowless variant) | — |
| Security Bit | Programmable security bit (per MAX 5000 family) | — |
| Tension d'alimentation | [DATA_NEEDED: VCC nominal and tolerance] | — |
| Type de montage | Through-hole (Pin Grid Array) | Surface Mount |
| Statut RoHS | Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) | [DATA_NEEDED: RoHS status] |
| Lifecycle | Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) | — |
| Programming Support | MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers | — |
| Logic Elements / Logic Array Blocks | — | [DATA_NEEDED: number of LABs] |
| Propagation Delay (tPD) | — | 40 ns |
| Maximum Operating Frequency | — | [DATA_NEEDED: fMAX value] |
| User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| Total Inputs / Outputs | — | 72 inputs / 64 outputs |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Nominal Supply Voltage | — | 5 V |
| Plage de température de fonctionnement | — | 0 °C to +70 °C (commercial) |
| Terminal Pitch | — | 0.635 mm |
| Technology | — | CMOS, UV-Erasable / OTP EPROM |
| Configuration Method | — | One-Time Programmable (OTP) / UV-Erasable |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |