EPM5192AJC-15 vs EPM5192AJC84-15 Vergleich

Detaillierter Direktvergleich von EPM5192AJC-15 von Intel und EPM5192AJC84-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192AJC-15 EPM5192AJC84-15
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,85 $18,95
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable Programmable Logic Device) EPLD (Erasable Programmable Logic Device)
Macrocells 192 192
Logic Capacity 100% connectivity, sum-of-products PLA architecture —
Pin-to-Pin Delay (tPD) 15 ns —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) 5 V (single supply)
Betriebstemperatur 0C to +70C (commercial) [DATA_NEEDED: commercial/industrial/military grade]
Gehäuse 84-pin PLCC (J-lead, ceramic, non-windowed) 84-pin PLCC (J84C) windowed ceramic
Montageart Surface Mount Surface Mount
Programmability UV-erasable (windowed variant) / One-Time-Programmable —
Toolchain MAX+PLUS II —
RoHS-Status [DATA_NEEDED: RoHS compliance] Non-compliant (contains Pb, ceramic windowed package)
Pin-Anzahl 84 —
User I/O Pins [DATA_NEEDED: user I/O count] —
Speed Grades Available -15, -20, -25 (this part: -15) —
Configuration Memory EPROM (UV-erasable) —
Propagation Delay (tpd) — 15 ns
Maximum Clock Frequency (fMAX) — 83.3 MHz
Technology — CMOS, UV-erasable EPROM
Programming Method — UV-erase + EPROM programming (windowed package)
Logic Blocks — 16 Logic Array Blocks (LABs)
I/O Pins — [DATA_NEEDED: user I/O count]
Process Technology — CMOS EPROM

Datenblätter & Ressourcen

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